In the semiconductor industry, there is a continuing trend toward higher device densities. To achieve these high densities there have been, and continue to be, efforts toward scaling down device dimensions (e.g., at sub-micron levels) on semiconductor wafers. In order to accomplish such high device packing densities, smaller and smaller feature sizes are required. This includes the width and spacing of interconnecting lines, spacing and diameter of contact holes, and the surface geometry, such as corners and edges, of various features. The dimensions of and between such small features can be referred to as critical dimensions. With an ever increasing number of integrated circuit features being formed on a circuit die, the importance of properly designing patterns to form structures that are isolated and non-interfering with one another has also increased.
Conventional semiconductor devices typically comprise a semiconductor substrate and a plurality of dielectric and conductive layers formed thereon. An integrated circuit contains numerous microelectronic devices, such as metal oxide semiconductor field effect transistors (MOSFETs), a plurality of conductive patterns comprising conductive lines separated by interwiring spacings, and a plurality of interconnect lines, such as bus lines, bit lines, word lines and logic interconnect lines. Such interconnection lines, made of metal interconnect materials, generally constitute a limiting factor in terms of size (width) and various functional characteristics of the integrated circuit.
With the increase in metal levels and line length, and the corresponding decreases in line width, there is a need in the art for systems and methods that improve critical dimensions and electrical performance of interconnect structures and conductive patterns.